The present invention relates to integrated circuit devices and, more particularly, to methods of forming a capacitor using an atomic layer deposition (ALD) process.
A cell capacitance of a semiconductor memory device may be decreased when a size of a cell region of the semiconductor memory device is reduced to change the integration density of the semiconductor memory device. The reduction of the cell capacitance typically deteriorates readability of the semiconductor memory device and increases a soft error rate of the device. As a result, the semiconductor memory device may not properly operate at a low voltage due to the reduction of the cell capacitance.
To improve the cell capacitance of the semiconductor memory device having a small cell region, it is know to form a dielectric layer having a very thin thickness. It is also known to form a lower electrode having a cylindrical shape or a fin shape. In a dynamic random access memory (DRAM) device having a storage capacity of above about 1 gigabyte, however, the above-mentioned approaches generally may be not employed for manufacturing a DRAM device having a desired cell capacitance.
To address the above-mentioned problems, it is also known to form a dielectric layer of a capacitor using a material having a high dielectric constant instead of silicon nitride, such as tantalum oxide (Ta2O5) or aluminum oxide (Al2O3). For example, the dielectric layer of the capacitor may be formed using yttrium oxide (Y2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), niobium oxide (Nb2O5), barium titanate (BaTiO3) or strontium titanate (SrTiO3). These metal oxides may be used for a dielectric layer of a capacitor in a semiconductor memory device having a design rule of below about 1 μm.
When hafnium oxide is used for manufacturing a dielectric layer of a metal-insulator-metal (MIM) capacitor or hafnium oxide and aluminum oxide are employed for a composite dielectric layer of a capacitor, these dielectric layers may have reduced equivalent oxide thickness (EOT).
In addition, when a lower electrode of a capacitor is formed using polysilicon, a silicon nitride (Si3N4) film may be additionally formed on the lower electrode so as to protect the lower electrode from oxidizing. Here, the dielectric layer of the capacitor may include the silicon nitride film and a metal oxide film. Further, the dielectric layer may be formed using an atomic layer deposition (ALD) process. However, when the silicon nitride film is interposed between the lower electrode and the metal oxide film, the silicon nitride film may have a significant effect on the EOT of the dielectric layer because silicon nitride generally has a dielectric constant of about 7 to about 8.